kaguya
359 lines
15 KiB
C
359 lines
15 KiB
C
#include "ioapic.h"
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#include "apic.h"
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#include "mm/vmm.h"
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#include "mm/memory.h"
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#include "libk/stdio.h"
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#include <uacpi/tables.h> /* uacpi_table_find_by_signature / uacpi_table_unref */
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#include "pic.h"
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/* ══════════════════════════════════════════════════════════════════════════
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* ACPI MADT structures
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* (Defined locally so we don't depend on uACPI's internal acpi.h layout.)
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* ══════════════════════════════════════════════════════════════════════════ */
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extern const PICDriver* g_Driver; // old pic driver
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bool g_IOAPIC = false; // IOAPIC enabled
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typedef struct {
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uint8_t signature[4]; /* "APIC" */
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uint32_t length;
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uint8_t revision;
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uint8_t checksum;
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uint8_t oem_id[6];
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uint8_t oem_table_id[8];
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uint32_t oem_revision;
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uint32_t creator_id;
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uint32_t creator_revision;
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/* --- MADT-specific -------------------------------------------------- */
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uint32_t local_apic_addr; /* Default LAPIC physical address (32-bit) */
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uint32_t flags; /* bit 0 = dual 8259 PICs present */
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/* followed by variable-length Interrupt Controller Structure entries */
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} __attribute__((packed)) madt_t;
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typedef struct {
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uint8_t type;
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uint8_t length;
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} __attribute__((packed)) madt_entry_hdr_t;
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/* Type 0: Processor Local APIC */
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typedef struct {
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madt_entry_hdr_t hdr;
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uint8_t uid;
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uint8_t apic_id;
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uint32_t flags; /* bit 0 = enabled */
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} __attribute__((packed)) madt_lapic_t;
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/* Type 1: I/O APIC */
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typedef struct {
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madt_entry_hdr_t hdr;
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uint8_t id;
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uint8_t reserved;
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uint32_t address; /* Physical MMIO base */
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uint32_t gsi_base; /* First GSI handled by this IOAPIC */
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} __attribute__((packed)) madt_ioapic_t;
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/* Type 2: Interrupt Source Override */
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typedef struct {
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madt_entry_hdr_t hdr;
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uint8_t bus; /* 0 = ISA */
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uint8_t source; /* ISA IRQ number */
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uint32_t gsi; /* Remapped GSI */
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uint16_t flags; /* bits [1:0] = polarity, bits [3:2] = trigger mode */
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} __attribute__((packed)) madt_iso_t;
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/* Type 4: Local APIC NMI */
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typedef struct {
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madt_entry_hdr_t hdr;
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uint8_t uid; /* 0xFF = all processors */
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uint16_t flags;
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uint8_t lint; /* 0 or 1 */
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} __attribute__((packed)) madt_nmi_t;
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/* ══════════════════════════════════════════════════════════════════════════
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* Internal state
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* ══════════════════════════════════════════════════════════════════════════ */
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typedef struct {
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volatile uint32_t *base; /* Virtual address of IOAPIC MMIO */
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uint32_t gsi_base;
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uint32_t gsi_count; /* Number of redirection entries */
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} ioapic_t;
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static ioapic_t g_ioapics[IOAPIC_MAX];
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static int g_ioapic_count = 0;
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/* ISA interrupt source overrides (max 16 ISA IRQs) */
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typedef struct {
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bool present;
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uint32_t gsi;
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bool active_low;
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bool level;
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} iso_t;
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static iso_t g_iso[16]; /* indexed by ISA IRQ (source) */
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/* ══════════════════════════════════════════════════════════════════════════
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* Low-level IOAPIC MMIO access
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*
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* The IOAPIC has two MMIO registers:
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* base+0x00 IOREGSEL – index register (write which register to access)
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* base+0x10 IOWIN – data window (read/write the selected register)
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* ══════════════════════════════════════════════════════════════════════════ */
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static uint32_t ioapic_read(const ioapic_t *io, uint8_t reg) {
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*((volatile uint32_t *)(io->base + (0x00 >> 2))) = reg;
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return *((volatile uint32_t *)(io->base + (0x10 >> 2)));
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}
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static void ioapic_write(const ioapic_t *io, uint8_t reg, uint32_t val) {
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*((volatile uint32_t *)(io->base + (0x00 >> 2))) = reg;
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*((volatile uint32_t *)(io->base + (0x10 >> 2))) = val;
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}
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/* ── Find which IOAPIC owns a given GSI ─────────────────────────────────── */
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static ioapic_t *ioapic_for_gsi(uint32_t gsi) {
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for (int i = 0; i < g_ioapic_count; i++) {
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ioapic_t *io = &g_ioapics[i];
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if (gsi >= io->gsi_base && gsi < io->gsi_base + io->gsi_count)
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return io;
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}
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return NULL;
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}
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/* ══════════════════════════════════════════════════════════════════════════
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* Public API
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* ══════════════════════════════════════════════════════════════════════════ */
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uint32_t ioapic_gsi_for_isa_irq(uint8_t isa_irq) {
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if (isa_irq < 16 && g_iso[isa_irq].present)
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return g_iso[isa_irq].gsi;
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return isa_irq;
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}
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void ioapic_redirect(uint32_t gsi, uint8_t vector, uint8_t dest_lapic,
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bool active_low, bool level, bool masked) {
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ioapic_t *io = ioapic_for_gsi(gsi);
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if (!io) {
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printf("[IOAPIC] No IOAPIC for GSI %u\n", gsi);
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return;
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}
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uint8_t idx = (uint8_t)(gsi - io->gsi_base);
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uint32_t lo = (uint32_t)vector
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| IOAPIC_RTE_DM_FIXED
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| (active_low ? IOAPIC_RTE_ACTIVE_LOW : 0)
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| (level ? IOAPIC_RTE_LEVEL : 0)
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| (masked ? IOAPIC_RTE_MASKED : 0);
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uint32_t hi = (uint32_t)dest_lapic << 24;
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/* Write high word first, then low (avoids momentary spurious delivery) */
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ioapic_write(io, IOAPIC_REDTBL_HI(idx), hi);
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ioapic_write(io, IOAPIC_REDTBL_LO(idx), lo);
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}
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void ioapic_mask_gsi(uint32_t gsi) {
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ioapic_t *io = ioapic_for_gsi(gsi);
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if (!io) return;
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uint8_t idx = (uint8_t)(gsi - io->gsi_base);
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uint32_t lo = ioapic_read(io, IOAPIC_REDTBL_LO(idx));
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ioapic_write(io, IOAPIC_REDTBL_LO(idx), lo | IOAPIC_RTE_MASKED);
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}
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void ioapic_unmask_gsi(uint32_t gsi) {
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ioapic_t *io = ioapic_for_gsi(gsi);
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if (!io) return;
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uint8_t idx = (uint8_t)(gsi - io->gsi_base);
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uint32_t lo = ioapic_read(io, IOAPIC_REDTBL_LO(idx));
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ioapic_write(io, IOAPIC_REDTBL_LO(idx), lo & ~IOAPIC_RTE_MASKED);
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}
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/* ══════════════════════════════════════════════════════════════════════════
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* Initialisation
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* ══════════════════════════════════════════════════════════════════════════ */
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void ioapic_init(void) {
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/*
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* ── Step 1: Find the MADT via uACPI ──────────────────────────────────
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*
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* The MADT signature in ACPI is "APIC" (not "MADT").
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* uacpi_table_find_by_signature returns a handle whose .ptr field points
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* to the raw table data in (HHDM-mapped) physical memory.
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*/
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struct uacpi_table madt_table;
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uacpi_status st = uacpi_table_find_by_signature("APIC", &madt_table);
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if (uacpi_unlikely_error(st)) {
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printf("[IOAPIC] Could not find MADT: %s\n", uacpi_status_to_string(st));
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return;
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}
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madt_t *madt = (madt_t *)madt_table.ptr;
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printf("[IOAPIC] MADT @ virt 0x%lx len=%u lapic_addr=0x%08x\n",
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(uint64_t)madt, madt->length, madt->local_apic_addr);
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/*
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* ── Step 2: Walk the MADT entry list ─────────────────────────────────
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*
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* Entries start immediately after the fixed 44-byte MADT header and run
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* until madt->length bytes from the table base.
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*/
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const uint8_t *entry_ptr = (const uint8_t *)madt + sizeof(madt_t);
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const uint8_t *madt_end = (const uint8_t *)madt + madt->length;
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while (entry_ptr < madt_end) {
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const madt_entry_hdr_t *hdr = (const madt_entry_hdr_t *)entry_ptr;
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if (hdr->length < 2) {
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printf("[IOAPIC] MADT entry with length < 2, stopping parse\n");
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break;
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}
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switch (hdr->type) {
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/* ── Type 0: Processor Local APIC ──────────────────────────────── */
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case 0: {
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const madt_lapic_t *e = (const madt_lapic_t *)entry_ptr;
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printf("[IOAPIC] MADT[0] Processor UID=%u LAPIC ID=%u flags=0x%x%s\n",
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e->uid, e->apic_id, e->flags,
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(e->flags & 1) ? "" : " (disabled)");
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break;
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}
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/* ── Type 1: I/O APIC ───────────────────────────────────────────── */
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case 1: {
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const madt_ioapic_t *e = (const madt_ioapic_t *)entry_ptr;
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if (g_ioapic_count >= IOAPIC_MAX) {
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printf("[IOAPIC] Too many IOAPICs, skipping ID=%u\n", e->id);
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break;
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}
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ioapic_t *io = &g_ioapics[g_ioapic_count];
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io->gsi_base = e->gsi_base;
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/*
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* Map the IOAPIC MMIO page. Like the LAPIC, the HHDM covers the
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* IOAPIC's physical address (typically 0xFEC00000) so we just add
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* MEM_PHYS_OFFSET. Two MMIO registers are accessed (offsets 0 and
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* 0x10) so one 4 KiB page is sufficient.
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*
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* TODO: Mark the page UC (cache-disable) in the PTE when VMM
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* gains support for PAT / PCD flags.
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*/
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uint64_t phys = (uint64_t)e->address;
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uintptr_t virt = (uintptr_t)phys + MEM_PHYS_OFFSET;
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/* The HHDM loop in vmm_init already covered this range; if not,
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* uncomment the explicit map call below: */
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/* vmm_map_page(kernel_pagemap, virt, phys,
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PAGE_READ | PAGE_WRITE | PAGE_NO_EXECUTE, Size4KiB); */
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io->base = (volatile uint32_t *)virt;
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/* Read version register to discover number of redirection entries */
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uint32_t ver = ioapic_read(io, IOAPIC_REG_VER);
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io->gsi_count = ((ver >> 16) & 0xFF) + 1; /* bits [23:16] = max entry index */
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printf("[IOAPIC] MADT[1] ID=%u phys=0x%08x GSI base=%u entries=%u\n",
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e->id, e->address, io->gsi_base, io->gsi_count);
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/*
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* ── Mask every redirection entry ─────────────────────────────
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*
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* We keep all entries masked at boot time. Legacy ISA IRQs are
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* handled by the i8259 → LAPIC LINT0 ExtINT path, not via the
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* IOAPIC. PCI devices can be connected later with ioapic_redirect().
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*/
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for (uint32_t n = 0; n < io->gsi_count; n++) {
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ioapic_write(io, IOAPIC_REDTBL_HI(n), 0);
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ioapic_write(io, IOAPIC_REDTBL_LO(n), IOAPIC_RTE_MASKED | 0xFF);
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}
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g_ioapic_count++;
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break;
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}
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/* ── Type 2: Interrupt Source Override ──────────────────────────── */
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case 2: {
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const madt_iso_t *e = (const madt_iso_t *)entry_ptr;
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/* flags bits [1:0]: 00/11 = conforms to bus (ISA = active high edge)
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* 01 = active high, 11 = active low
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* flags bits [3:2]: 00/11 = conforms to bus (ISA = edge)
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* 01 = edge, 11 = level */
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bool active_low = ((e->flags & 0x3) == 3);
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bool level = ((e->flags >> 2) & 0x3) == 3;
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printf("[IOAPIC] MADT[2] ISA IRQ %u -> GSI %u %s %s\n",
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e->source, e->gsi,
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active_low ? "active-low" : "active-high",
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level ? "level" : "edge");
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if (e->source < 16) {
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g_iso[e->source].present = true;
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g_iso[e->source].gsi = e->gsi;
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g_iso[e->source].active_low = active_low;
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g_iso[e->source].level = level;
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}
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break;
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}
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/* ── Type 4: Local APIC NMI ─────────────────────────────────────── */
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case 4: {
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const madt_nmi_t *e = (const madt_nmi_t *)entry_ptr;
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printf("[IOAPIC] MADT[4] NMI UID=0x%02x LINT%u\n",
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e->uid, e->lint);
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break;
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}
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default:
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printf("[IOAPIC] MADT entry type=%u length=%u (skipped)\n",
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hdr->type, hdr->length);
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break;
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}
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entry_ptr += hdr->length;
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}
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uacpi_table_unref(&madt_table);
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printf("[IOAPIC] Init done: %d IOAPIC(s) found\n", g_ioapic_count);
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}
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void irq_redirect_to_apic(uint8_t isa_irq, uint8_t vector,
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uint8_t dest_lapic, bool masked)
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{
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if (isa_irq >= 16) {
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printf("[IRQ] irq_redirect_to_apic: ISA IRQ %u out of range\n", isa_irq);
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return;
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}
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uint32_t gsi = ioapic_gsi_for_isa_irq(isa_irq);
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/* Get polarity/trigger from MADT ISO or use ISA defaults */
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bool active_low = false;
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bool level = false;
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if (isa_irq < 16 && g_iso[isa_irq].present) {
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active_low = g_iso[isa_irq].active_low;
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level = g_iso[isa_irq].level;
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} else {
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/* Standard ISA: active-high, edge-triggered (except some like IRQ0/8) */
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if (isa_irq == 0 || isa_irq == 8) {
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level = true; /* often level on real hardware */
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}
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}
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/* Mask in the 8259 so it stops firing through LINT0 */
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if (g_Driver) {
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g_Driver->Mask(isa_irq);
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}
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/* Programme IOAPIC redirection entry */
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ioapic_redirect(gsi, vector, dest_lapic,
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active_low, level, masked);
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printf("[IRQ] Redirected ISA IRQ %u -> GSI %u vector 0x%02x LAPIC %u %s %s\n",
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isa_irq, gsi, vector, dest_lapic,
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active_low ? "active-low" : "active-high",
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level ? "level" : "edge");
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g_IOAPIC = true;
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} |