kaguya
133 lines
7.0 KiB
C
133 lines
7.0 KiB
C
#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "arch/x86_64/bus/pci.h"
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/* ── HDA MMIO register offsets ─────────────────────────────────────────────── */
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#define HDA_GCAP 0x00 /* u16 Global Capabilities */
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#define HDA_VMIN 0x02 /* u8 Minor Version */
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#define HDA_VMAJ 0x03 /* u8 Major Version */
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#define HDA_OUTPAY 0x04 /* u16 Output Payload Capability */
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#define HDA_INPAY 0x06 /* u16 Input Payload Capability */
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#define HDA_GCTL 0x08 /* u32 Global Control */
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#define HDA_WAKEEN 0x0C /* u16 Wake Enable */
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#define HDA_STATESTS 0x0E /* u16 State Change Status (one bit per codec) */
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#define HDA_GSTS 0x10 /* u16 Global Status */
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#define HDA_INTCTL 0x20 /* u32 Interrupt Control */
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#define HDA_INTSTS 0x24 /* u32 Interrupt Status */
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#define HDA_WALCLK 0x30 /* u32 Wall Clock Counter */
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#define HDA_SSYNC 0x38 /* u32 Stream Synchronisation */
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/* CORB */
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#define HDA_CORBLBASE 0x40 /* u32 CORB Lower Base Address */
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#define HDA_CORBUBASE 0x44 /* u32 CORB Upper Base Address */
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#define HDA_CORBWP 0x48 /* u16 CORB Write Pointer */
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#define HDA_CORBRP 0x4A /* u16 CORB Read Pointer */
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#define HDA_CORBCTL 0x4C /* u8 CORB Control */
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#define HDA_CORBSTS 0x4D /* u8 CORB Status */
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#define HDA_CORBSIZE 0x4E /* u8 CORB Size */
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/* RIRB */
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#define HDA_RIRBLBASE 0x50 /* u32 RIRB Lower Base Address */
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#define HDA_RIRBUBASE 0x54 /* u32 RIRB Upper Base Address */
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#define HDA_RIRBWP 0x58 /* u16 RIRB Write Pointer (hardware-maintained)*/
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#define HDA_RINTCNT 0x5A /* u16 Response Interrupt Count */
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#define HDA_RIRBCTL 0x5C /* u8 RIRB Control */
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#define HDA_RIRBSTS 0x5D /* u8 RIRB Status */
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#define HDA_RIRBSIZE 0x5E /* u8 RIRB Size */
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/* Stream Descriptor register offsets (relative to the SD's MMIO base) */
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#define HDA_SD_CTL0 0x00 /* u8 Control byte 0 (SRST, RUN, IOCE …) */
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#define HDA_SD_CTL1 0x01 /* u8 Control byte 1 */
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#define HDA_SD_CTL2 0x02 /* u8 Control byte 2 bits[7:4] = stream tag */
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#define HDA_SD_STS 0x03 /* u8 Status bit2=BCIS bit3=FIFOE bit4=DESE */
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#define HDA_SD_LPIB 0x04 /* u32 Link Position in Buffer */
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#define HDA_SD_CBL 0x08 /* u32 Cyclic Buffer Length */
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#define HDA_SD_LVI 0x0C /* u16 Last Valid Index */
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#define HDA_SD_FIFOS 0x10 /* u16 FIFO Size (read-only) */
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#define HDA_SD_FMT 0x12 /* u16 Format */
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#define HDA_SD_BDPL 0x18 /* u32 BDL Lower Base Address */
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#define HDA_SD_BDPU 0x1C /* u32 BDL Upper Base Address */
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#define HDA_SD_STRIDE 0x20 /* Each stream descriptor is 0x20 bytes wide */
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/* GCTL bits */
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#define HDA_GCTL_CRST (1u << 0) /* Controller Reset (0 = reset, 1 = run) */
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#define HDA_GCTL_UNSOL (1u << 8) /* Accept Unsolicited Responses */
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/* SD CTL byte-0 bits */
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#define HDA_SD_CTL_SRST (1u << 0) /* Stream Reset */
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#define HDA_SD_CTL_RUN (1u << 1) /* Stream Run */
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#define HDA_SD_CTL_IOCE (1u << 2) /* Interrupt on Completion Enable */
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#define HDA_SD_CTL_FEIE (1u << 3) /* FIFO Error Interrupt Enable */
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#define HDA_SD_CTL_DEIE (1u << 4) /* Descriptor Error Interrupt Enable */
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/* SD STS bits */
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#define HDA_SD_STS_BCIS (1u << 2) /* Buffer Completion Interrupt Status */
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#define HDA_SD_STS_FIFOE (1u << 3) /* FIFO Error */
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#define HDA_SD_STS_DESE (1u << 4) /* Descriptor Error */
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/* Codec widget types (from AUDIO_WIDGET_CAP bits[23:20]) */
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#define HDA_WTYPE_AUDIO_OUT 0x0
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#define HDA_WTYPE_AUDIO_IN 0x1
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#define HDA_WTYPE_AUDIO_MIXER 0x2
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#define HDA_WTYPE_AUDIO_SEL 0x3
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#define HDA_WTYPE_PIN 0x4
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/* Codec parameter IDs (used with GET_PARAM verb 0xF00) */
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#define HDA_PARAM_VENDOR_ID 0x00
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#define HDA_PARAM_NODE_COUNT 0x04
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#define HDA_PARAM_FUNC_GROUP_TYPE 0x05
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#define HDA_PARAM_AUDIO_WIDGET_CAP 0x09
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#define HDA_PARAM_SUPPORTED_PCM 0x0A
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#define HDA_PARAM_PIN_CAPABILITIES 0x0C
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#define HDA_PARAM_CONN_LIST_LEN 0x0E
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#define HDA_PARAM_AMP_CAP_OUTPUT 0x12
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/* Pin capability bits */
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#define HDA_PINCAP_OUTPUT (1u << 4)
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#define HDA_PINCAP_INPUT (1u << 5)
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/* ── Types ─────────────────────────────────────────────────────────────────── */
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typedef struct {
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uint32_t sample_rate;
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uint8_t channels; /* 1 = mono, 2 = stereo */
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uint8_t bits_per_sample; /* 8 / 16 / 20 / 24 / 32 */
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} hda_format_t;
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/* Buffer Descriptor List entry (must be 128-byte aligned; page-aligned is fine) */
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typedef struct __attribute__((packed)) {
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uint64_t addr; /* Physical address of the audio buffer */
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uint32_t length; /* Length in bytes */
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uint32_t flags; /* Bit 0 = IOC (Interrupt on Completion) */
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} hda_bdl_entry_t;
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/* ── Public API ─────────────────────────────────────────────────────────────── */
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/**
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* hda_init - find, map, and initialise the first HDA controller on the bus.
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* @dev: PCI device struct returned by pci_find_hda().
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* Returns true on success.
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*/
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bool hda_init(pci_device_t *dev);
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/**
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* hda_play_pcm - set up an output stream and start playback.
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* @phys_buf : physical address of the audio data (from pmm_alloc).
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* @size : byte count of the audio data.
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* @fmt : sample rate / channel count / bit depth.
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* Returns true if the stream was started successfully.
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*/
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bool hda_play_pcm(uintptr_t phys_buf, uint32_t size, hda_format_t fmt);
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/**
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* hda_wait_complete - block until the current stream finishes (polls BCIS).
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* Stops and resets the stream when done.
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*/
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void hda_wait_complete(void);
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/** hda_stop - immediately stop the output stream. */
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void hda_stop(void);
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/** hda_is_playing - returns true while the stream is running and not done. */
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bool hda_is_playing(void); |