feat: implement PCI subsystem and integrate uACPI support

See previous commit

Signed-off-by: kaguya <vpshinomiya@protonmail.com>

src/mm/vmm.c

@@ -279,17 +279,45 @@ level4:
 		return NULL;
 	}
 
-	//	spinlock_drop(&pagemap->lock);
+	spinlock_drop(&pagemap->lock);
 	return &pml1[pml1_entry];
 }
 
 
 uint64_t vmm_virt_to_phys(struct pagemap *pagemap, uint64_t virt) {
-	spinlock_acquire_or_wait(&pagemap->lock);
-	uint64_t *pte = vmm_virt_to_pte(pagemap, virt, false);
-	spinlock_drop(&pagemap->lock);
-	if (pte == NULL || (((*pte) & ~0xffffffffff000) & 1) == 0)
-		return INVALID_PHYS;
+    spinlock_acquire_or_wait(&pagemap->lock);
 
-	return ((*pte) & 0xffffffffff000);
+    size_t pml4_entry = (virt & ((uint64_t)0x1FF << 39)) >> 39;
+    size_t pml3_entry = (virt & ((uint64_t)0x1FF << 30)) >> 30;
+    size_t pml2_entry = (virt & ((uint64_t)0x1FF << 21)) >> 21;
+    size_t pml1_entry = (virt & ((uint64_t)0x1FF << 12)) >> 12;
+
+    uint64_t *pml4 = pagemap->top_level;
+
+    uint64_t *pml3 = get_next_level(pml4, pml4_entry, false);
+    if (!pml3) goto fail;
+
+    uint64_t *pml2 = get_next_level(pml3, pml3_entry, false);
+    if (!pml2) goto fail;
+
+    // Check for 2MiB huge page (PS bit = bit 7)
+    if (pml2[pml2_entry] & (1 << 7)) {
+        uint64_t phys = (pml2[pml2_entry] & ~0x1FFFFFULL) // 2MiB-aligned base
+                      + (virt & 0x1FFFFFULL);             // + offset within 2MiB
+        spinlock_drop(&pagemap->lock);
+        return phys;
+    }
+
+    uint64_t *pml1 = get_next_level(pml2, pml2_entry, false);
+    if (!pml1 || !(pml1[pml1_entry] & 1)) goto fail;
+
+    uint64_t phys = (pml1[pml1_entry] & 0x000ffffffffff000ULL)
+                  + (virt & 0xFFFULL);
+    spinlock_drop(&pagemap->lock);
+    return phys;
+
+fail:
+    spinlock_drop(&pagemap->lock);
+    printf("Invalid Phys!\n");
+    return INVALID_PHYS;
 }