user: implement mlibc as the libc, finally.

It's finally done..

Signed-off-by: kaguya <vpshinomiya@protonmail.com>

src/main.c

@@ -98,6 +98,68 @@ static void hcf(void) {
     }
 }
 
+static inline void cpuid(uint32_t leaf, uint32_t subleaf,
+                         uint32_t *eax, uint32_t *ebx,
+                         uint32_t *ecx, uint32_t *edx) {
+    asm volatile ("cpuid"
+        : "=a"(*eax), "=b"(*ebx), "=c"(*ecx), "=d"(*edx)
+        : "a"(leaf), "c"(subleaf));
+}
+
+int cpu_has_leaf7() {
+    uint32_t a, b, c, d;
+    cpuid(0, 0, &a, &b, &c, &d);
+    return a >= 7;
+}
+
+int cpu_has_fsgsbase() {
+    if (!cpu_has_leaf7())
+        return 0;
+
+    uint32_t a, b, c, d;
+    cpuid(7, 0, &a, &b, &c, &d);
+
+    return (b & (1u << 0)) != 0;
+}
+
+static inline uint64_t read_cr4(void) {
+    uint64_t val;
+    __asm__ volatile ("mov %%cr4, %0" : "=r"(val));
+    return val;
+}
+
+
+static inline void write_cr4(uint64_t val) {
+    asm volatile ("mov %0, %%cr4" :: "r"(val));
+}
+
+static inline uint64_t read_cr0(void) {
+    uint64_t val;
+    __asm__ volatile ("mov %%cr0, %0" : "=r"(val));
+    return val;
+}
+
+static inline void write_cr0(uint64_t val) {
+    __asm__ volatile ("mov %0, %%cr0" :: "r"(val));
+}
+
+
+#define CR4_FSGSBASE (1ULL << 16)
+
+
+
+void enable_fsgsbase_if_supported() {
+    if (!cpu_has_fsgsbase()) {
+        // fallback: don't use wrfsbase
+        printf("FSGSBASE not supported, skipping wrfsbase/wrgsbase\n");
+        return;
+    }
+
+    uint64_t cr4 = read_cr4();
+    cr4 |= CR4_FSGSBASE;
+    write_cr4(cr4);
+}
+
 extern struct kernel_pagemap;
 uint64_t g_rsdp_phys;
 
@@ -128,6 +190,31 @@ static uacpi_interrupt_ret handle_power_button(uacpi_handle ctx) {
 }
 
 
+
+
+
+void init_simd(void) {
+    uint64_t cr0 = read_cr0();
+    uint64_t cr4 = read_cr4();
+
+    // --- CR0 setup ---
+    cr0 &= ~(1 << 2);   // Clear EM (Emulation) → allow FPU/SSE
+    cr0 |=  (1 << 1);   // Set MP (Monitor Coprocessor)
+    cr0 &= ~(1 << 3);   // Clear TS (Task Switched) → no #NM
+
+    // --- CR4 setup ---
+    cr4 |= (1 << 9);    // OSFXSR → enable FXSAVE/FXRSTOR + SSE
+    cr4 |= (1 << 10);   // OSXMMEXCPT → enable SSE exceptions
+
+    write_cr0(cr0);
+    write_cr4(cr4);
+
+    // Initialize FPU/SSE state
+    __asm__ volatile ("fninit");
+    
+}
+
+
 void kmain(void) {
     if (LIMINE_BASE_REVISION_SUPPORTED(limine_base_revision) == false) { 
         hcf();
@@ -354,6 +441,9 @@ void kmain(void) {
 
     sched_init();
 
+    enable_fsgsbase_if_supported();
+    init_simd();
+
     start_userspace();
 
     sched_yield();